Wire bonds are commonly utilized for connecting integrated circuitry associated with semiconductor constructions to other circuitry external of the constructions. An exemplary prior art method of forming a wire bond for a semiconductor construction is described with reference to FIGS. 1-7.
Referring initially to FIG. 1, a semiconductor construction 10 is illustrated at a preliminary processing stage of the prior art method. Construction 10 comprises a semiconductor substrate 12 which includes a base 14, a conductive material 16 supported by the base, and an electrically insulative cap 18 over the conductive material.
Base 14 can comprise a semiconductor material, such as, for example, a monocrystalline silicon wafer having numerous integrated circuit devices (not shown) supported thereby.
Conductive material 16 can correspond to, for example, a metal-containing level formed over and in electrical connection with various integrated circuit devices associated with base 14. Conductive material 16 can, for example, correspond to the so-called level 1, level 2, level 3, level 4, level 5, etc. metal layers commonly associated with semiconductor constructions. In particular aspects, conductive material 16 can comprise, consist essentially of, or consist of aluminum and/or copper. In such aspects, material 16 can, for example, comprise one or more alloys comprising one or both of copper and aluminum. Conductive material 16 has an upper surface 17.
Insulative material 18 is a protective material formed over the uppermost surface of conductive material 16, and can comprise any suitable insulative material or combination of insulative materials. In particular aspects, insulative material 18 will comprise, consist essentially of, or consist of one or both of silicon nitride and silicon dioxide. For instance, insulative material 18 can comprise a homogeneous layer of silicon dioxide or silicon nitride. Alternatively, material 18 can comprise a multi-layer stack, with particular layers being silicon dioxide and other layers being silicon nitride. Insulative material 18 has an uppermost surface 19 (the label “19” is shown in FIG. 4).
Substrate 12 can be referred to as a semiconductor substrate. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. In accordance with the definition of substrate provided above, all of the structures 14, 16 and 18 can be together considered to correspond to a semiconductor substrate. Alternatively, structure 14 can be considered to alone correspond to a semiconductor substrate. As yet another alternative, structure 14 and structure 16 can be considered to correspond to a semiconductor substrate, with structure 18 being considered to be formed over such semiconductor substrate.
A patterned radiation-imageable material 20 is formed over the uppermost surface 19 of insulative material 18. Radiation-imageable material 20 can correspond to photoresist, and can be photolithographically formed into the shown pattern. The photolithographic patterning of material 20 would typically comprise exposure of material 20 to a pattern of radiation, with such radiation being suitable to render exposed portions of material 20 either more or less soluble than non-exposed portions of the material in a solvent. The material 20 is then exposed to the solvent to remove the more soluble portions and thus form the shown pattern. The shown patterned material 20 has an opening 22 extending therethrough to an upper surface of insulative material 18.
Referring next to FIG. 2, the opening 22 is extended through insulative material 18 to an upper surface of conductive material 16 with an appropriate etch.
Referring next to FIG. 3, patterned material 20 (FIG. 2) is removed.
Referring next to FIG. 4, a patterned protective material 30 is formed over insulative material 18. In some aspects, insulative material 18 can be considered a passivation layer (or layers), and material 30 can be considered a protective cap formed over the passivation layer (or layers). Material 30 can correspond to a photolithographically patterned radiation-imageable material, and in some aspects comprise, consist essentially of, or consist of polyimide. The patterned material 30 defines an opening 32 extending to an upper surface of material 18. Opening 32 is wider than the opening 22 described previously (FIG. 3).
FIG. 5 is a top view of the FIG. 4 construction, and shows the wide opening 32 entirely surrounding narrow opening 22. Openings 22 and 32 are shown having rectangular peripheries, but it is to be understood that the openings can be formed in any suitable configuration, including, for example, configurations with curved peripheries.
Referring next to FIG. 6, a tool 40 is utilized to bond a wire 42 to conductive material 16. The wire 42 is retained within a capillary 44 of tool 40, and accordingly the tool can be referred to as a bonder capillary tool. The bonding of wire 42 to material 16 is accomplished by contacting the wire onto the upper surface 17 of material 16 with typically known in the art ultrasonic, thermal or other energy to weld the wire 42 and material 16 together. The region of material 16 where wire 42 connects with the material can be referred to as a wire bonding region of the material 16, and is indicated by the label 43 in FIG. 6. More specifically, a wire bonding region of material 16 is the portion of material 16 that ultimately directly contacts wire 42 in forming a bond to the wire. The wire can comprise, for example, gold.
Tool 40 has a shown lower portion proximate material 16, and such portion has a lateral width 50. Such lateral width which can be referred to as the lateral footprint of tool 40 proximate a bonding region. In the shown aspect of the prior art, such lateral footprint problematically extends over masking material 30 and accordingly the masking material is smashed downwardly by tool 40 during the bonding of wire 42 to material 16. The smashing of material 30 leads to smashing of the underlying material 18, which forms a damage regions 52 of material 18. The damage region can problematically contain cracks or other undesired structural flaws.
Referring to FIG. 7, tool 40 is removed to leave wire 42 bonded to the wire bonding region of material 16. Unfortunately, the damaged regions of materials 30 and 18 remain after removal of the tool. Accordingly, it is desired to develop new methods for forming wire bonds which alleviate formation of damaged regions within materials 30 and 18.
Although only one wire bond is shown formed in the diagrams of FIGS. 1-7, it should be understood that a large number of wire bonds is typically formed over a single substrate, with each wire bond being fabricated with the methodology of FIGS. 1-7.
A continuing goal of semiconductor processing is to reduce photomasking steps, in that each photomasking step carries with it a risk of mask misalignment and defect creation. Accordingly, it is desired to develop methodologies of forming wire bonds which reduce photomasking steps relative to the number of steps utilized in the processing sequence of FIGS. 1-7.
Although the invention was motivated, at least in part by the problems discussed above, the invention is not limited to solutions of such problems.